1. Field of the Invention
The present invention relates to a bipolar transistor and a method of fabricating the same, and more particularly, to a bipolar transistor having an emitter and a collector diffusion layer in the sidewalls and the bottom of a device isolation trench and a method of fabricating the same.
2. Background of the Related Art
Due to a great interest in a composite semiconductor, whose memory and logic are formed within a single chip, its usage is increasing. Because the composite semiconductor device can integrate memory and logic into a single chip and manufacture the same in a single process, it can operate faster and use less electric power than existing combinations of chips without any substantial change of design.
On the other hand, as the manufacturing processes of memory products and logic products are simultaneously performed, the size of the single chip is getting larger and, therefore, there are a lot of difficulties in conducting the manufacturing process. In addition, the transistor in the memory focuses on prevention of leakage current rather than providing a high current driving force. On the other hand, logic product transistors sometimes require a high current driving force. Such mixed function products (i.e., containing both memory and logic) need to be manufactured with both characteristics.
An example of a conventional method of fabricating bipolar transistors in semiconductor devices is illustrated in the accompanying drawings, in which FIG. 1 is a top view of a bipolar transistor in a conventional composite semiconductor, and FIG. 2 is a cross -sectional view of the conventional bipolar transistor along the line A-A′ in FIG. 1.
As illustrated in FIG. 1 and FIG. 2, after the formation of a device isolation region in a semiconductor substrate, an N-type well 10 is formed in a predetermined region of the semiconductor substrate and a P-type well 11 having a predetermined depth is formed in the N-type well 10. Here, the thickness of the P-type well 11 is generally between 1 and 1.2 μm. Therefore, it is difficult to realize the transistor that has a high amplification gain. On the other hand, a DRAM bit line that will be formed in a later process can not be formed in the P-type junction because it uses N-type doped silicon. Therefore, the first N+ region 14 is formed in the P-type well 11. After the source/drain junction of a DRAM transistor is formed, or P+ region 13 is formed in the P-type well 11, the second N+ region 12 is formed for collector pick-up in the N-type well 10.
Metal contacts are formed respectively for the first and second N+ regions 14 and 12 and the P+ region 13 in the later processes (not shown), which function as an emitter, a base and a collector, respectively. That is, the first N+ region 14 becomes the emitter, the P+ region 13 becomes the base, and the second N+ region 12 becomes the collector.
Although the existing method of fabricating the bipolar transistor as described above integrates both the memory and the logic as a semiconductor device into a single chip and in a single process, it is difficult to make a transistor that has a high amplification gain because of the depth of well, and to form both the emitter and the collector that have deep junction depth because of limitations on the source/drain diffusion layer that are formed in the memory transistors at the same time. Therefore, a direct current amplification factor (hfe) and/or the implantation efficiency of holes is low.